Surface inspecting method and surface inspecting apparatus

ABSTRACT

Provided is a surface inspecting method for inspecting a surface of a semiconductor substrate having linear line patterns repeatedly arranged and hole-shaped hole patterns formed on the line patterns. The surface inspecting method has a setting step (S 101 ) of setting inspecting conditions; an illuminating step (S 102 ) of irradiating the surface of the semiconductor substrate with illuminating step under the inspecting conditions set in the setting step; a detecting step (S 103 ) of detecting diffracted light from the semiconductor substrate irradiated with illumination light; and an inspecting step (S 104 ) of inspecting existence/nonexistence of a defect on the hole patterns, based on the diffracted light detected in the detecting step. In the setting step, the inspecting conditions are to be set so that the travelling direction of illumination light on the surface of the semiconductor substrate is different from the repeated arrangement direction of the line patterns and that such travelling direction substantially matches the repeated arrangement direction of the hole patterns.

This is a continuation of PCT International Application No.PCT/JP2009/057232, filed on Apr. 8, 2009, which is hereby incorporatedby reference. This application also claims the benefit of JapanesePatent Application No. 2008-101367, filed in Japan on Apr. 9, 2008,which is hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to a surface inspecting method and surfaceinspecting apparatus to inspect a surface of a wafer or the like in asemiconductor manufacturing process.

TECHNICAL BACKGROUND

As a semiconductor device, a memory element such as a DRAM (DynamicRandom Access Memory), a flash memory (storage device) and a devicecalled a logic element having a storing section and a processing sectionare available. In recent years, a pattern for a semiconductor devicetends to become increasingly fine and minute due to a trend of highspeed processing, less power consumption, and increased storage capacityand, therefore, a demand for inspection of a defect occurring in amanufacturing process of semiconductor devices becomes severer at thesame time. A defocus defect occurring in the exposure process inparticular is a largest factor of defective products. The defocus defectrefers to swelling of a wafer surface caused by foreign matters existingbetween a rear surface of a semiconductor wafer and a wafer stage whichoccurs at time of an exposure process and, as a result, a pattern linewidth and/or pattern diameter value being called a CD (CriticalDimension) value is out of dimensional tolerance resulting in patterndefects. Moreover, in a scanning-type exposure machine in particular, afocus change occurs in an exposure shot due to a focusing error whichcauses the CD value to be out of tolerance, also resulting in a defectin a pattern.

As an apparatus to automatically inspect a defocus defect, an apparatusto detect a defect in a pattern has been in practical use which isconfigured to irradiate a surface of a semiconductor wafer withillumination light to receive diffracted light from a repeating patternon the surface of the wafer and to utilize a change in an amount ofdiffracted light occurring in the diffracted light from a defectiveportion (the change occurs due to difference in CD values) (see, forexample, Patent Reference 1). The diffracted light is produced from apattern of a repeating arrangement and its state depends onrepeatability (cycle called an arrangement or a pitch). As asemiconductor device is becoming increasingly fine and minute, arepeating cycle of the repeating pattern (pitch) naturally becomessmaller and, in a memory device such as a DRAM, a transistor and/orcapacitor has to be disposed in a small cell area and the arrangement ofa repeating pattern (hole pattern) of a hole called a contact holeincluding a bit contact, capacitor contact (or called a storage nodecontact), cylinder contact (storage capacitor) and the like in one cellis two dimensional. Then, one cell further has an arrangement repeatedtwo-dimensionally and, therefore, most of the surface of a memory deviceis occupied by two-dimensional repeating patterns.

CITATION LIST Patent Document

Patent Reference 1: Japanese Laid-Open Patent Publication No.2006-105951

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

When such the inspection apparatus to inspect a hole pattern is used, asin the case of the inspection of a linear repeating pattern (linepattern), due to a reason that many patterns have repeatability in 0 or90 degree direction, an attempt to find out diffraction condition outfor these two azimuth angles has been made. However, such inspectingconditions are not always the optimum conditions for the inspection of ahole pattern.

The present invention has been made in light of problems described aboveand has an object to provide a surface inspecting method and surfaceinspecting apparatus which enable the inspection of a hole patternaccording to the most optimized inspecting conditions.

Means to Solve the Problems

To achieve such an object, a surface inspecting method of the 1stinvention is the method for inspecting a surface of a semiconductorsubstrate having a line-shaped line pattern and a hole-shaped holepattern formed on the line pattern, each being arranged repeatedlyincluding a first step of setting an irradiating direction ofillumination light on a surface of the semiconductor substrate, a secondstep of irradiating the surface of the semiconductor substrate withillumination light from the irradiating direction set at the first step,a third step of detecting diffracted light corresponding to a bit of thehole pattern from the surface irradiated with the illumination light,and a fourth step of detecting existence/non-existence of a defectoccurring in the hole pattern based on the diffracted light detected atthe third step and in the first step, the irradiating direction beingset so that a traveling direction of the illumination light on thesurface of the semiconductor substrate is different from a repeatingarrangement direction of the line pattern and substantially matches arepeating arrangement direction of the hole pattern.

It is preferable that, in the first step of the above surface inspectingmethod, the irradiating direction is set so that a travelling directionof the illumination light on the surface of the semiconductor substrateis different from the repeating arrangement direction of the linepattern and the diffracted light an amount of which greatly changesdepending on a change in a shape of the hole pattern occurs.

It is preferable that, in the first step of the surface inspectingmethod, the irradiating direction is set by performing simulation of achange in an amount of the diffracted light according to a change inshape of the hole pattern based on one of designing information of thehole pattern and shape measurement information of a hole pattern whoseshape has been measured in advance.

A surface inspecting method of the second invention is the method forinspecting a surface of a semiconductor substrate having a hole-shapedpattern including a first step of setting an irradiating direction of anillumination light to be applied to a surface of the semiconductorsubstrate, a second step of irradiating the surface of the semiconductorsubstrate with illumination light from the irradiating direction set atthe first step, a third step of detecting diffracted light correspondingto a pitch of the hole pattern to be applied from the surface irradiatedwith the illumination light, and a fourth step of inspectingexistence/non-existence of a defect in the hole pattern based on thediffracted light detected at the third step, wherein, in the first step,the irradiating direction is set by performing simulation of a change inan amount of diffracted light according to a change in shape of the holepattern so that the diffracted light an amount of which changes greatlyaccording to a change in shape of the hole pattern occurs.

It is preferable that, in the first step of the surface inspectingmethod, simulation of a change in an amount of the diffracted light isperformed according to a change in shape of the hole pattern based onone of designing information about the hole pattern and shapemeasurement information about a hole pattern whose shape has beenmeasured in advance.

It is preferable that, in the first step of the surface inspectingmethod, the irradiating direction is set so that the diffracted light anamount of which changes greatly according to a change in shape of thehole pattern occurs and that diffracted light is not easily producedform a layer on a side being lower than the hole pattern.

A surface inspecting apparatus of the first invention is the apparatusfor inspecting a surface of a semiconductor substrate having aline-shaped line pattern and a hole-shaped hole pattern formed on theline pattern including a setting section to set an irradiating directionof illumination light on a surface of the semiconductor substrate, anilluminating section to irradiate the surface of the semiconductorsubstrate with illumination light from the irradiating direction set bythe setting section, and a detecting section to detect diffracted lightcorresponding to a bit of the hole pattern from the surface irradiatedwith the illumination light, and an inspecting section of detectingexistence/non-existence of a defect occurring in the hole pattern basedon the diffracted light detected by the inspecting section, wherein thesetting section sets the irradiating direction so that a travelingdirection of the illumination light on the surface of the semiconductorsubstrate is different from a repeating arrangement direction of theline pattern and substantially matches a repeating arrangement directionof the hole pattern.

It is preferable that, in the surface inspecting apparatus, the settingsection sets the irradiating direction so that the travelling directionof the illumination light on the surface of the semiconductor substrateis different from the repeating arrangement direction of the linepattern and the diffracted light an amount of which greatly changesdepending on a change in a shape of the hole pattern occurs.

It is preferable that, in the surface inspecting apparatus according,the setting section sets the irradiating direction by performingsimulation of a change in an amount of the diffracted light according toa change in shape of the hole pattern based on one of designinginformation about the hole pattern and shape measurement informationabout a hole pattern whose shape has been measured in advance.

A surface inspecting apparatus of the second invention is an apparatusfor inspecting a surface of a semiconductor substrate having ahole-shaped pattern including a setting section to set an irradiatingdirection of an illumination light to be applied to a surface of thesemiconductor substrate, an illuminating section to irradiate a surfaceof the semiconductor substrate with illumination light from theirradiating direction set by the setting section, a detecting section todetect diffracted light corresponding to a pitch of the hole pattern tobe applied from the surface irradiated with the illumination light, andan inspecting section to inspect existence/non-existence of a defect inthe hole pattern based on the diffracted light detected by the detectingsection, wherein the setting section sets the irradiating direction byperforming simulation of a change in an amount of diffracted lightaccording to a change in shape of the hole pattern so that thediffracted light an amount of which changes greatly according to achange in shape of the hole pattern occurs.

It is preferable that, in the surface inspecting apparatus, the settingsection performs simulation of a change in an amount of the diffractedlight according to a change in shape of the hole pattern based on one ofdesigning information about the hole pattern and shape measurementinformation about a hole pattern whose shape has been measured inadvance.

It is preferable that, in the surface inspecting apparatus, the settingsection sets the irradiating direction so that the diffracted light anamount of which changes greatly according to a change in shape of thehole pattern occurs and that diffracted light is not easily producedform a layer on a side being lower than the hole pattern.

ADVANTAGEOUS EFFECTS OF THE INVENTION

According to the present invention, a hole pattern can be inspectedaccording to the optimum inspecting conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an entire configuration of the surfaceinspection apparatus of the present invention.

FIG. 2 is a control block diagram of an inspecting condition determiningsection.

FIG. 3 is a schematic diagram showing a wafer image.

FIGS. 4A, 4B, and 4C are plan views of a wafer.

FIG. 5 is a partial cross-sectional view of a wafer.

FIG. 6 is a schematic diagram showing a field process.

FIG. 7 is a schematic diagram showing a gate process.

FIG. 8 is a schematic diagram showing a cell contact process.

FIG. 9 is a schematic diagram showing a bit contact process.

FIG. 10 is a schematic diagram showing a bit line process.

FIG. 11 is a schematic diagram showing a capacitor contact.

FIG. 12 is a schematic diagram showing a cylinder process.

FIG. 13 is a flowchart showing the surface inspection method of thepresent invention.

FIGS. 14A, 14B, and 14C are diagrams obtained by modeling a line andspace pattern.

FIG. 15 is a graph showing a relation between a distance from 0th orderdiffracted light and an amount of diffracted light.

FIG. 16 is a graph showing a relation between duty and a change in anamount of diffracted light.

FIG. 17 is a plan view of an FEM (Focus Exposure Matrix) wafer.

FIGS. 18A and 18B are diagrams showing one example of a luminance map.

FIGS. 19A and 19B are diagrams showing one example of a luminance map.

FIG. 20 is a diagram showing a result from an FFT (Fast FourierTransform) processing performed on a bit contact model.

FIG. 21 is a diagram showing a result from FFT processing performed on abit contact model.

FIG. 22A to 22D are diagrams showing diffraction light distribution in amoving radius direction in FIG. 21.

FIG. 23 is a diagram obtained by modeling a capacitor contact process.

FIG. 24 a diagram showing a result from FFT processing performed on acapacitor contact model.

FIGS. 25A, 25B, and 25C are diagrams showing diffracted lightdistribution in a moving radius direction in FIG. 24.

FIG. 26 is a diagram obtained by modeling a cell contact process.

FIG. 27 a diagram showing a result from FFT processing performed on acell contact model.

FIGS. 28A, 28B, 28C, and 28D are diagrams showing diffracted lightdistribution in a moving radius direction in FIG. 27.

FIG. 29 is a diagram showing a model obtained by contracting by 20% thecell contact in FIG. 26.

FIG. 30 is a diagram showing a result from FFT processing performed onthe model in FIG. 29.

FIGS. 31A, 31B, 31C, and 31D are diagrams showing diffracted lightdistribution in a moving radius direction in FIG. 30.

FIG. 32 is a diagram showing an arrangement direction and a pitch of thecell contact.

FIG. 33 is a control block diagram of an inspecting conditiondetermining section of a modified example.

FIGS. 34A, 34B, and 34C are diagrams obtained by modeling a bit contact.

FIGS. 35A, 35B, and 35C are diagrams showing a result from FFTprocessing performed on the bit contact model.

FIG. 36 is a graph showing a relation between a change in CD value and achange in an amount of diffracted light.

FIG. 37 is a diagram obtained by modeling a field process.

FIG. 38 is diagram showing a result from FFT processing performed on themodel in FIG. 37.

FIGS. 39A and 39B are schematic diagrams showing a gate process of aflash memory.

FIG. 40 is a schematic diagram showing a gate line of a flash memory.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention isdescribed by referring to drawings. The surface inspecting apparatus 1of the present embodiment is shown in FIG. 1 and mainly includes a waferholding section 10, an illuminating section 20, a detecting section 30,an image processing section 40, an inspecting section 41, an inspectingcondition setting section 42, an FEM evaluating section 43, and aninspecting condition determining section 45. Moreover, in the presentembodiment, the direction perpendicular to the paper surface of FIG. 1is defined as an X direction, a horizontal direction is defined as a Ydirection, a vertical direction is defined as a Z direction, and arotational direction in an XY plane is defined as a θ direction.

The wafer holding section 10 has a stage 11 on which a semiconductorwafer 50 (hereinafter, simply the wafer 50) is put, a θ rotating section12 to rotate the stage 11 in the θ direction, and a tilting section 13to tilt the stage 11. The stage 11 holds, by vacuum adsorption or thelike, the wafer 50 put on an upper surface of the stage 11 by using anunillustrated conveying apparatus. The stage 11 holding the wafer 50 canbe rotated in the θ direction using an axis adapted to pass through thecenter of the wafer 50 (center of the stage 11) and to be perpendicularto the surface of the wafer 50 as a rotational axis. Also, the stage 11is so configured to be tiltable, by the tilting section 13, about theaxis (axis parallel to the X direction) passing through the surface ofthe wafer 50 and to adjust the incident (and outgoing) angle of theillumination light 25.

The illuminating section 20 has a light source 21, a wavelengthselecting section 22, and an illuminated mirror 23 and is configured soas to irradiate a surface of the wafer 50 with illumination light 25. Asthe light source 21, a mercury lamp is used. Therefore, the lightemitted from the light source 21 contains a plurality of rays of lighteach having a wavelength λ, for example, an e-line (λ=546 nm), g-line(λ=436 nm), h-line (λ=405 nm), j-line (λ=313 nm), and a ray having thewavelengthλ of about 250 nm and only the ray of light having a specifiedwavelength out of these rays of light is selected by a wavelengthselecting section 22 so as to be allowed to transmit through thewavelength selecting section 22. The light transmitted through thewavelength selecting section 22 is reflected by the illuminated mirror23 to become collimated flux which serves as the illumination light 25to illuminate the wafer 50. The illumination light 25 becomes lighthaving a wavelength of monochromatic light at the wavelength selectingsection 22 and becomes collimated flux at the illuminated mirror 23 and,therefore, parallel rays of the diffracted light 35 are produced from arepeating arrangement pattern of the wafer 50.

The detecting section 30 for detecting the diffracted light 35 from thewafer 50 is so configured to have a light receiving mirror 31, a lightreceiving lens 32, and a photography section 33. The rays of thediffracted light 35, after being gathered by the light receiving mirror31, reach a photographic surface of the photography section 33 throughthe light receiving lens 32 and forms an image of the wafer 50 on thephotographic surface. As a result, the image of the surface of the wafer50 is formed on the photographic surface of the photography section 33.The photography section 33 photoelectrically converts the image of thesurface of the wafer 50 formed on the photographic surface to generateimage signals and outputs the image signals to the image processingsection 40. By configuring as above, the image of the surface (allsurfaces) of the wafer 50 can be collectively photographed and,therefore, scanning of the surface of the wafer 50 is not required, thusenabling the surface of the wafer 50 to be inspected at high speed.

As shown in FIG. 3, the image processing section 40, based on the imagesignals of the wafer 50 inputted from the photography section 33,converts the image of the wafer 50 into a digital image with specifiedbits (for example, 8 bits). The image processing section 40 stores theimage A1 of a non-defective wafer (wafer having no defects) into anunillustrated data base in order to use the image A1 as a template andthen compares the image A1 with the inspected image A2 of the wafer 50to be inspected, which is obtained through the photographic process byusing the photography section 33. At this point of time, on the wafer 50having a defect, an amount of diffracted light changes only in a portionof the defect K. Therefore, the inspecting section 41 connectedelectrically to the image processing section 40 makes a judgment aboutwhether there is a defect based on the result from the comparison(change in the amount of diffracted light) between the inspected imageA2 and non-defective wafer image A1. As a result, when it is judged bythe inspecting section 41 that there is a defect on the surface of thewafer 50, a defect judged image A3 showing a region kA of a shot 51containing the defect in a highlighted manner, out of a plurality ofshots 51, 51, . . . arranged on the surface of the wafer 50, isgenerated by the image processing section 40 and is displayed, togetherwith the judgment result, on an unillustrated displaying section.Moreover, the image A1 of a non-defective wafer may be stored in a database not only for every process for the wafer 50 but also for each of aplurality of inspecting conditions in the same process. Furthermore, theimage data on the inspected image A2 can be outputted from the imageprocessing section 40 to the FEM evaluating section 43 to calculate theaverage luminance of the inspected image A1 for every exposure shot,which is described later.

The inspecting condition setting section 42 makes the θ rotating section12 and tilting section 13 set the stage 11 by rotating the stage 11 by θdegrees and by tilting the stage 11 so that the stage 11 has a specifiedazimuth (rotation angle θ of the stage 11 relative to a notch or thelike) and a tilt angle (angle at which the stage 11 is tilted from ahorizontal state) at which the diffracted light 35 can be detected. Therelation between the repeated arrangement pattern to be formed on thesurface of the wafer 50 and diffracted light 35 is explained byreferring to FIGS. 4A to 4C. FIG. 4A is a plan view obtained when thewafer 50 is seen from its upper side, in which it is assumed that thewafer 50 is put in parallel to the XY plane. As shown in FIG. 4A, theillumination light 25 is incident to the wafer 50 in a slanted mannerusing the surface being parallel to the YZ plane as an incident surface.Then, it is assumed that the repeated arrangement pattern 52 formed onthe surface of the wafer 50 is a simple line and space pattern.Moreover, the direction in which the repeated arrangement pattern 52extends is defined as an arrangement direction 55 of the repeatedarrangement pattern 52 and the direction being perpendicular to thearrangement direction is defined a repeating direction 56 of therepeated arrangement pattern 52.

In the case of FIG. 4A, the arrangement direction 55 is the X directionand the repeating direction 56 is the Y direction and, therefore, thediffracted light 35 is produced within a surface being parallel to theYZ plane. On the other hand, as shown in FIG. 4B, in the case of arepeated arrangement pattern 52′ in which the repeating direction is theX direction, while the illumination light 25 is incident to the wafer 50in a slanted manner using the surface being parallel to the YZ plane asan incident surface, the diffracting light is not produced in thesurface being parallel to the YZ plane. However, as shown in FIG. 4C,when the wafer 50 held by the stage 11 is rotated by θ (90) degrees(relative to the notch 53) by using the θ rotating section 12, therepeating direction of the repeated arrangement pattern 52′ becomes theY direction and, therefore, the diffracted light 35 is produced within asurface being parallel to the YZ plane.

As shown in FIG. 1, since the optical system (illumination system 20)applying the illumination light 25, together with the optical system(detecting section 30) detecting the diffracted light 35, is disposedwithin a surface being parallel to the YZ plane, through the θ rotationof the wafer 50 by the θ rotating section 12, regardless of thedirection of the repeated arrangement pattern, the stage 11 can be setat any azimuth angle at which the diffracted light can be received. Onthe other hand, in the case of the diffracted light to be produced on asurface being parallel to the YZ plane, a diffraction angle (angleformed between the illumination light 25 and diffracted light 35)differs depending on a cycle period (pitch) of the repeated arrangementpattern 52. According to optical principles, the smaller the pitchbecomes, the larger the diffraction angle of 1st order diffracted lightbecomes. Therefore, the inspecting condition setting section 42 allowsthe tilting section 13 to tilt the stage 11 (wafer 50) so that thediffracted light 35 can be reliably received by the light receivingmirror 31. Since the tilt angle can be calculated theoretically from thepitch of the repeated arrangement pattern 52 and the wavelength of theillumination light 25, if the repeating direction 56 of the repeatedarrangement pattern (line and space pattern) 52 and the pitch are known,the inspecting condition determining section 45 can determine inspectingconditions such as a azimuth angle and/or tilt angle and can input theseobtained conditions into the inspecting condition setting section 42 forsetting.

As is understood from the above description, when the arrangementinformation is already known, the determination of inspecting conditionsby the inspecting condition determining section 45 is easy. Next, theprocessing to be performed by the inspecting condition determiningsection 45 is described. As shown in FIG. 2, the inspecting conditiondetermining section 45 is made up of an arrangement data inputtingsection 46, a CD value change converting section 47 connectedelectrically to the arrangement data inputting section 46, a diffractedlight simulator section 48 connected electrically to the CD value changeconverting section 47, and an inspecting condition data outputtingsection 49 connected electrically to the diffracted light simulatorsection 48.

In the case shown in FIG. 4A, the arrangement direction 55 of therepeated arrangement pattern (line and space pattern) 52 is the Xdirection and the repeating direction 56 is the Y direction.Furthermore, if the repeating pitch is, for example, 0.2 μm and theratio between a line and a space (hereinafter simply “duty”) is 1:1,such arrangement information (information that the arrangement directionis the X direction, repeating direction is the Y direction, repeatingpitch is 0.2 μm, duty is 1:1, and the like) is first inputted into thearrangement data inputting section 46 for being stored. The abovearrangement information may be CAD (Computer Aided Design) data of areticle, however, the surface inspecting apparatus 1 of the presentembodiment is related to the defect inspection of the wafer 50 and,therefore, it is needless to say that the arrangement information ispreferably a value being near the value obtained after the process ofbeing exposure-transferred onto the wafer 50. For example, even when theduty is 1:1, the duty changes depending on whether an amount of exposure(dose) is large or small relative to a specified dose amount and,therefore, the arrangement information (duty) may be corrected by usinga measured value of an actual SEM (Scanning Electron Microscope) or thelike.

The CD value, which is a line width in the case of the line and spacepattern and is a diameter of a hole in the case of the hole pattern, hasnecessarily a tolerance. Too slender line causes breakage and too thickline causes leakage current. The CD value is regulated from viewpointsthat too small hole diameter induces contact failure and too large holediameter induces leakage current. Therefore, in the CD value changeconverting section 47, a changed CD value obtained by changing the CDvalue is virtually set, for example, the CD value is set by using valueswithin ±5%, ±10%, ±15%, ±20%, ±25%, and the like of a designed CD valuecalculated based on arrangement information stored in the arrangementdata inputting section 46. Then, the CD value change converting section47 inputs the designed CD value and changed CD value into the diffractedlight simulator section 48. The diffracted light simulator section 48(described later) basically determines inspecting conditions using FFTprocessing by which diffracted light is calculated by performing asimulation. Next, the diffracted light simulator section 48 outputsresults from the processing as inspecting condition data which is thenoutputted to the inspecting condition setting section 45 through theinspecting condition data outputting section 49.

Next, manufacturing processes of the semiconductor wafer 50 (DRAM) to beinspected are described by referring to FIGS. 5 to 12. Moreover, detailsof manufacturing processes are disclosed in Japanese Laid-Open PatentPublication Nos. 2001-185701, 2006-319121, 2007-287794 and the like. Inthe present embodiment, only the important critical processes (processfor higher device density) for the defect inspection by using adiffracted method is described.

The field process, as shown in FIGS. 5 and 6, is a first criticalprocess to form an active area 60 and a field (element separationregion) 61. In the semiconductor wafer (DRAM) of F=90 nm or F=70 nm, thearrangement direction 62 a of the active area 60 is tilted by 72 degreesrelative to the X direction and the direction perpendicular to thearrangement direction 62 a is the repeating direction 62 b of the activearea 60. In the present embodiment, F denotes a working dimension (thatis, a half of the pitch of a gate or a word line). On the other hand,when the field 61 is noted, it can be thought that there is anarrangement direction 63 a of 45 degree direction in a clearance betweenthe active areas 60 arranged in the direction being tilted 72 degreesrelative to the X direction and the direction perpendicular to thearrangement direction 63 a is a repeating direction 63 b. It can be alsothought that there is an arrangement direction 64 a in a clearancebetween the active areas 60 and the Y direction perpendicular to thearrangement direction 64 a is a repeating direction 64 b having a longcycle.

After the completion of the field process, non-critical processesincluding 5 to 10 processes such as a doping process, ion implantationprocess, CVD (Chemical Vapor Deposition) process are performed and,then, the next gate process begins. The gate process, as shown in FIGS.5 and 7, is a critical process of forming a gate 65 serving as a wordline. The gate 65 is the line and space pattern and, in general, theduty between the line 66 and space 67 is 1:1. The arrangement directionof the gate 65 is the X direction and the repeating direction is the Ydirection.

After the completion of the gate process, non-critical processesincluding 5 to 10 processes such as a doping, ion implantation, CVDprocess, and the like are performed, and then transistors (not shown)are formed and then the next cell contact process is performed. The cellcontact process, as shown in FIGS. 5 and 8, is a critical hole processwith two aims of forming cell contacts (hole) 70 for the bit contact andcapacitor contact. It can be said that, the critical hole process, outof the processes of manufacturing the DRAM, is the most dense and closeprocess. In the cell contact 70, an arrangement direction 71 a in the Xdirection, arrangement direction 72 a in the 72 degree direction,arrangement direction 73 a in the −45 degree direction can be easilyfound from FIG. 8 and each of the directions perpendicular to these is,respectively, a repeating direction 71 b for the arrangement direction71 a in the X direction, repeating direction 72 b for the arrangementdirection 72 a in the 72 degree direction, and the repeating direction73 b in the −45 degree direction. Moreover, though there may be otherrepeating arrangements and details are described by referring to FIG.26. Furthermore, the cell contact 70 is connected at the position beingoffset from the position of the capacitor contact to be described laterand, therefore, has an elliptical shape and its short diameter directionmatches the arrangement direction 72 a in the 72 degree direction.

The subsequent bit contact process, as shown in FIGS. 5 and 9, is acritical hole process of forming a bit contact 75 connected to the cellcontact 70 and a bit line to be described. In the cell contact 75, anarrangement direction 76 a in the −45 degree direction, arrangementdirection 77 a in the zero degree direction (X direction), arrangementdirection 78 a in the 90 degree (Y direction) direction can be easilyfound from FIG. 9 and each of the directions perpendicular to these is,respectively a repeating direction 76 b for the arrangement direction 76a in the −45 degree direction, repeating direction 77 b for thearrangement direction 77 a in the zero degree direction (X direction),and repeating direction 78 b for the arrangement direction 78 a in the90 degree direction (Y direction). Moreover, though there may be otherrepeating arrangements, details are described by referring to FIG. 20.

The subsequent bit line process, as shown in FIGS. 5 and 10, is acritical process of forming a bit line 80 orthogonal to the gate 65(word line) to be connected to the bit contact 75. The arrangementdirection of the gate 65 is the X direction (repeating direction is theY direction) and, therefore, the arrangement direction of the bit line80 is the Y direction (repeating direction is the X direction). The bitline 80 is the line and space pattern and, in general, the duty betweenthe line and space is 1:1. The arrangement direction of the gate 65 isthe X direction and its repeating direction is the Y direction.

The capacitor contact process, as shown in FIGS. 5 and 11, is a criticalhole process of forming a capacitor contact 85 to be connected to thecell contact 70 and a cylinder (capacitor) to be described later. In thecapacitor contact 85, an arrangement direction 86 a in the −45 degreedirection, arrangement direction 87 a in the zero degree direction (Xdirection), arrangement direction 88 a in the 90 degree direction (Ydirection) can be easily found from FIG. 11 and each of the directionsperpendicular to these is, respectively, a repeating direction 86 b forthe arrangement direction 86 a in the −45 degree direction, repeatingdirection 86 b for the arrangement direction 87 a in the zero degree (Xdirection), and repeating direction 88 b for the arrangement direction88 a in the 90 degree direction (Y direction). Moreover, though theremay be other repeating arrangements, details are described by referringto FIG. 23.

The cylinder process, as shown in FIGS. 5 and 12, is a critical holeprocess of forming a cylinder 90 to be connected to the capacitorcontact 85. The cylinder 90 has an arrangement direction 91 a in thedegree direction, arrangement direction 92 a in the 72 degree direction,arrangement direction 93 a in the 18 degree direction and each of thedirections perpendicular to these is, respectively, a repeatingdirection 91 b for the arrangement direction 91 a in the −45 degreedirection, repeating direction 92 b for the arrangement direction 92 ain the 72 degree direction, and repeating direction 93 b for thearrangement direction 93 a in the 18 degree direction. In addition, thecylinder 90 is a capacitor to accumulate electric charges and,therefore, has a comparatively large diameter and a large depth inparticular. Furthermore, it is necessary that there is an equal intervalamong the cylinders 90 being adjacent to one other and that thecylinders are disposed densely and, therefore, the position of thecapacitor contact 85 is offset from the position of the cell contact 70and the positions of the capacitor contacts 85 are offset from oneanother and, therefore, the cell contact 70 is allowed to have anelliptical shape. After the cylinder process, in general, a wiringprocess begins.

The surface inspecting method for semiconductor wafers 50 is describedby referring to a flow chart shown in FIG. 13. First, in Step S101,inspecting conditions such as an azimuth angle or tilt angle(illuminating direction of the illumination light 25 on the surface ofthe wager 50) are set. In the setting process, the inspecting conditionsetting section 42 makes the θ rotating section 12 and tilting section13 set an azimuth angle and tilting angle so as to meet the inspectingconditions. Also, the inspecting condition setting section 42 can makethe wavelength selecting section 22 select an illuminating wavelengthwhich satisfies the inspecting conditions. Moreover, the inspectingconditions are determined by the FEM evaluating section 43 or theinspecting condition determining section 45 and details are describedlater.

In a subsequent Step S102, according to the inspecting conditions(azimuth, tilt angle, and the like) set in the Step S101, the surface ofthe wafer 50 is irradiated with the illumination light 25. In theilluminating process, light emitted from the light source 21 of theilluminating section 20 transmits through the wavelength selectingsection 22 and is reflected by the illuminated mirror 23 and becomes theillumination light 25 being collimated flux and is applied to thesurface 50. The illumination light 25 becomes light having a wavelengthof monochromatic light at the wavelength selecting section 22 andbecomes collimated flux at the illuminated mirror 23 and, therefore,parallel rays of the diffracted light 35 are produced from the repeatedarrangement pattern of the wafer 50.

In a subsequent Step S103, the diffracted light 35 from the surface ofthe wafer 50 irradiated with the illumination light 25 is detected. Inthe detecting process, the rays of the diffracted light 35, after beinggathered by the light receiving mirror 31 of the detecting section 30,reach a photographic surface of the photography section 33 through thelight receiving lens 32 and forms an image of the wafer 50 on thephotographic surface and the image is photographed by the photographysection 33. The photography section 33 converts photoelectrically theimage on the surface of the wafer 50 formed on the photographic surfaceinto image signals and outputs the image signal to the image processingsection 40.

In a subsequent Step S104, based on the diffracted light detected in theStep S103, the existence/nonexistence of defects in a pattern ischecked. In the inspection process, the image processing section 40,based on the image signal of the wafer 50 inputted from the photographysection 33, compares an inspected image A2 with a non-defective waferimage A1 (see FIG. 3) and also based on results from the comparison(change in an amount of the diffracted light), the inspecting section 41judges whether there is a defect or not on the wafer 50. As a result, ifit is judged by the inspecting section 41 that there is a defect on thesurface of the wafer 50, a defect judged image A3 (see FIG. 3) isproduced by the image processing section 40 and is then displayed,together with judgment results, in an unillustrated displaying section.

In the conventional inspecting apparatus, when inspecting conditions areto be determined, it is assumed that, as is represented by the line andspace pattern, there are many patterns each having repeatability in a 0degree direction or 90 degree direction and, therefore, the diffractioncondition is simply found by using these two azimuths and thediffraction condition is applied also in the hole process. That is,light is applied at the azimuth of 0 degree to check whether thediffracted light can be obtained and the same is then performed at theazimuth of 90 degrees and, if some rays of diffracted light areobtained, the applied condition is registered as an inspecting conditionto inspect the semiconductor wafers produced in quantity. Therefore, acase occurs where the inspection is made without knowing from whichlayer, out of a plurality of layers formed on the surface of a wafer, orwithout knowing from which arrangement pattern the diffracted light isreceived. There was, therefore, a fear that the inspection was made in anot-optimized state where diffracted light was received from a lowerlayer and/or where a change in the CD value could not be detectedsensitively.

Additionally, the conventional inspecting technology presents a problemthat, due to application of process for higher density to a patternmanufacturing which makes an arrangement pitch smaller, it is madeimpossible to obtain diffracted light. As the arrangement pitch becomessmaller, diffracted light is produced in an angle direction being farfrom the angle of the illumination light and, when the angle becomes farrelative to the angle of the illumination light, it is practicallyimpossible to receive the diffracted light.

As described above, it seems that an arrangement direction and repeatingdirection can be found easily from arrangement information of a patternin the manufacturing process of the wafer 50, however, it is difficultto judge as to which repeating direction of diffracted light can providethe optimum inspecting conditions. This is because the optimuminspecting conditions enabling sensitive defect detection of a change inCD value cannot be determined due to an unknown repeating pitch and dueto the occurrence of not only 1st order diffracted light but also 2ndand more higher order diffracted light. Hereinafter, a method fordetermining inspecting conditions in the setting process of the presentembodiment is described in detail.

First, the case where the CD value is changed in the line and spacepattern is explained as the simplest example by referring to FIGS. 14A,14B, and 14C to 16. FIG. 14A is an explanation model having a pitch with80 pixels in which the line 101 (white) with 40 pixels and the space 102(black) with 40 pixels are arranged repeatedly in a horizontallyrepeating direction. The model shown in FIG. 14A is a model of anon-defective wafer having the duty between the line 100 and space 102being 1:1 and the information about the arrangement of the model of thenon-defective wafer is stored in the arrangement data inputting section46 (see FIG. 2).

The model shown in FIG. 14B is the model having the line (white) with 30pixels and space (black) with 50 pixels and the model shown in FIG. 14Cis the model having the line (white) with 20 pixels and space (black)with 60 pixels. Therefore, the duty of each of the models shown in FIG.14A, FIG. 14B, and FIG. 14C is, respectively, 4:4, 3:5, and 2:6.Moreover, the models shown in FIGS. 14B and 14C are set by the CD valuechange converting section 47. Furthermore, in FIGS. 14A to 14C, noarrangement direction is shown for shorted expression of the models.

The diffracted light simulator section 48 performs the FFT processing onthe models shown in FIGS. 14A to 14C (based on a designed CD value and achanged CD value obtained by the CD value change converting section 47).As the software for the FFT processing, “Scion Image” manufactured byScion Corp. or “Image Pro” manufactured by Media Cybernetics Co., can beused. FIG. 15 shows changed values after the FFT processing with therepeating direction as an abscissa. The abscissa in FIG. 15 shows adistance from a point of origin (0th order diffracted light) and thelarger values represent that the diffracted light is more far from the0th order diffracted light. The ordinate shows values each correspondingrespectively to (not proportional to) an amount of diffracted light andthe smaller values represent that the diffracted light is bright.

In FIG. 15, each valley existing near to the values 6, 13, and 19 on theordinate shows respectively the 1st order diffracted light, 2nd orderdiffracted light, and 3rd order diffracted light. FIG. 15 shows that, inthe line and space pattern (model of non-defective wafer) having theduty of 1:1 (in the case where the duty is 4:4 in the presentcalculation), the 2nd order diffracted light is not produced opticallyand theoretically, however, as is apparent from FIG. 15, in the case ofthe curve having the duty of 4:4, no valley exists near to the value 13on the abscissa and the 2nd diffracted light is not produced. Also, the3rd diffracted light occurs for every duty, however, an amount ofdiffracted light is smaller than that of the 1st diffracted light.However, if the amount of the 3rd diffracted light is decreased to aboutone tenth or one hundredth level compared with the 1st diffracted light,it presents a problem from the viewpoint of detection accuracy. However,the ratio of the amount of the 3rd diffracted light shown in FIG. 15 tothe amount of the 1st diffracted light is not large enough to produceany problem.

Now, the detection sensitivity to the CD value change, which is mostimportant, is evaluated. This evaluation is performed by the CD valuechange converting section 47 and diffracted light simulator section 48.The CD value change is a phenomenon that occurs in so-called defocusdefects in many cases and, in the semiconductor manufacturing process,irrespective of the cause for the occurrence, the CD value is the valueto be severely controlled. In order to evaluate the detectionsensitivity to the CD value change, as shown in FIG. 16, the change inan amount of the 1st and 2nd order diffracted light corresponding to achange in the duty is first to be observed. In FIG. 16, the duty (4:4for non-defective wafer, 3:5, and 2:6) is plotted as abscissa and aratio (relative value) of each amount of diffracted light to the amountof diffracted light obtained when the duty is 4:4 as ordinate. In thecase of the 1st order diffracted light, when the duty is 4:4, 3:5, and2:6 in FIG. 15, the values on the ordinate are 10, 14, and 21respectively and, therefore, in FIG. 16, when the duty is 3:5 and 2:6,absolute values are 14/10=1.4 and 21/10=2.1, respectively. The samecalculation can be also applied to the 3rd order diffracted light.

As is understood from FIG. 16, the amount of the 1st order diffractedlight changes almost linearly in response to the change in the CD valueof a line width. On the other hand, the amount of the 3rd orderdiffracted light changes non-linearly, however, the change in the amountof diffracted light is large when the duty is 3:5 and, therefore, solong as this point is concerned, the 3rd order diffracted light is moresensitive compared with the 1st order diffracted light. However, thediffraction angle (angle formed by incident light and diffracted light)of the 3rd diffraction angle is larger by about 3 times than that of the1st diffracted light. In the DRAM of 2F=about 0.14 μm which is called a“70 nm generation DRAM”, when practical light source wavelength andoptical placement are considered, if the pitch is 0.14 μm, the 3rddiffracted light cannot be received. Therefore, in this case, theinspecting condition is determined by the diffracted light simulatorsection 48 so that the 1st diffracted light which is practically optimumlight can be received and the determined inspecting condition data isoutputted from the inspecting condition data outputting section 49 tothe inspecting condition determining section 42. Then, the inspectingcondition determining section 42 tilts the stage 11 (wafer 50) so thatthe receipt of the 1st order diffracted light as the inspectingcondition determined by the inspecting condition determining section 45can be realized.

Thus, it has been found by calculation evaluation of sensitivity to thechange in amounts of diffracted light corresponding to the CD valuechange that there is the case in which higher order diffracted light(3rd diffracted light in the case shown in FIG. 16) can more sensitivelydetect the CD value change compared with the 1st diffracted light andthis fact can be effectively used as a judgment standard for determiningthe optimum inspecting condition. Details are described later.

Now, another method for determining inspecting conditions sensitive tothe CD value change, that is, the FEM evaluation to be performed by theFEM evaluating section 43 is described by referring to FIGS. 17 to 19Aand 19B. The FEM evaluating section 43 determines inspecting conditionsby using a wafer prepared for evaluation.

The wafer for evaluation, as shown in FIG. 17, is called an “FEM wafer110” on which exposure conditions are changed stepwisely for every rowand every column of the exposure shot 111. More specifically, in theshots (rows) arranged in up and down directions, exposure is performedby changing a dose amount (exposure energy) and, in the shots (columns)arranged in left and right directions, exposure is performed by changingan amount of focus offset. The CD value of the FEM wafer 110 is measuredfor every exposure shot, which is used for evaluating optimum exposureconditions for a semiconductor wafer and optimum process margin (processwindow). For example, in the case of an ArF exposing machine, an optimumdose condition is determined by the CD value obtained based on themeasurement using the SEM or the like, however, in the case where thedose amount is 40 mJ/cm², exposure is performed by setting the doseamount to be 35 mJ/cm² for the shot located on the uppermost row and theexposure is continued by decreasing the dose amount by 1 mJ/cm² forevery lower row. As a result, the dose amount becomes 35, 36, 37, . . ., 45 mJ/cm² in each shot and, on the row 112 being a central shot, thedose amount becomes 40 mJ/cm² being the optimum dose amount. On theother hand, as a result from the measurement of CD values by the SEM orthe like, if the optimum focus condition (focus margin) is −0.2 μm to+0.15 μm, the exposure is performed by setting the focus step to be 0.05μm and adding the focus step of −0.3, −0.25, . . . , +0.20 μm to everycolumn on the right side sequentially from the shot located on aleft-end column.

In order to determine inspecting conditions by using the FEM wafer 110as described above, the surface of the FEM wafer 110 is irradiated withthe illumination light 25 by using the illuminating section 20 shown inFIG. 1 and the diffracted light 35 is detected from the FEM wafer 110 byusing the detecting section 30 to obtain an inspected image of the FEMwafer 110. For example, when the FEM wafer 110 is used for inspectingthe bit contact 75 shown in FIG. 9, the arrangement direction is −45degree direction or 0 degree direction (or 90 degree direction).Moreover, the bit contact 75 is connected to the bit line 80 and,therefore, the arrangement pitch can be handled as being already knownbased on the arrangement pitch of the bit line. Based on the arrangementinformation described above, inspecting conditions are set by theinspecting condition setting section 42 to obtain the inspected image ofthe FEM wafer 110.

The inspected image (image signal) of the FEM wafer 110 is inputted fromthe image processing section 40 to the FEM evaluating section 43 wherean average luminance within a shot is calculated for every exposure shot111. It is assumed, for example, that an illumination map shown in FIG.18A under the condition for obtaining diffracted light from 0 degreedirection 77 a is obtained and that an illumination map shown in FIG.19A under the condition for obtaining diffracted light from −45 degreedirection 76 a (see FIG. 9) is obtained (light and shade of the exposureshot 111 in each drawing represents the degree of luminance). At thispoint of time, a shot receiving the optimum dose amount (40 mJ/cm²) isthe row 112 of the central shot and the graphs in FIGS. 18B and 19B canbe obtained by calculating average luminance at each shot in the row 112of the central shot for graphing curved-line approximation. Valuesobtained by swinging the focus in the row 112 in the central shot (shotreceiving the optimum dose amount) are plotted as abscissa shown inFIGS. 18B and 19B. Namely, the values correspond to the focus off-set of“−0.3, −0.25, . . . +0.20 μm”. The average luminance in each shot isplotted as ordinate.

As is apparent from FIGS. 18B and 19B, the CD value change produced bythe focus offset is more sensitively detected as the change in theamount of diffracted light in the luminance change (FIG. 19B) occurredwhen conditions for obtaining diffracted light from −45 degreearrangement direction 76 a are used as the inspecting condition, inspite of the same wafer, rather than in the luminance change (FIG. 18B)occurred when conditions for obtaining diffracted light from the 0degree arrangement direction 77 a are used as the inspecting conditions.

Then, such judgment is automatically made (through numerical calculationor the like) by the FEM evaluating section 43 and the condition forobtaining diffracted light form the −45 degree arrangement direction 76a is determined as the inspecting condition and the determinedinspecting condition data is outputted to the inspecting conditionsetting section 42.

The method is described for determining inspecting conditions accordingto the evaluation of the arrangement direction (or repeating direction)performed by the FEM evaluating section 43 and inspecting conditiondetermining section 45 from the arrangement information about repeatingarrangement pattern. FIG. 20 is a modeled diagram of the bit contact 75shown in FIG. 9 and it is assumed that the arrangement information aboutthe bit contact 75 is stored in the arrangement data inputting section46. As shown in FIG. 20, the bit contact 75 has the arrangementdirection 121 a in the 0 degree direction, arrangement direction 122 ain the 90 degree direction, arrangement direction 123 a in the −45degree direction, arrangement direction 124 a in the 45 degreedirection, arrangement direction 125 a in the 72 degree direction, andarrangement direction 126 a in the 18 degree direction.

FIG. 21 shows a diagram obtained by performing FTF processing on themodel in FIG. 20 by using the diffracted light simulator section 48 andby displaying a region near to a point of origin in an enlarged manner.In FIG. 21, rays of diffracted light 121 b to 126 b are shown eachcorresponding respectively to the arrangement direction 121 a in the 0degree direction, arrangement direction 122 a in the 90 degreedirection, arrangement direction 123 a in the −45 degree direction,arrangement direction 124 a in the 45 degree direction, arrangementdirection 125 a in the 72 degree direction, and arrangement direction126 a in the 18 degree direction. The center of FIG. 21 is a point oforigin and, when light having a specific wavelength enters, from adirection perpendicular to the paper surface, the repeating arrangementpattern as shown in FIG. 20, the diffracted light pattern passingthrough the pupil surface on a reflecting surface side or transmittingsurface side can be FIG. 21. Therefore, the center of FIG. 21 (point oforigin) corresponds to 0th order diffracted light (regularly reflectedlight). The direction directing toward the rays of diffracted light 121b to 126 b from the center of FIG. 21 is a repeating direction (asdescribed above, the repeating direction is perpendicular to anarrangement direction). Moreover, the distance from the center of FIG.21 (point of origin) to the rays of diffracted light 121 b to 126 bcorresponds to a diffraction angle.

The diffracted light receivable range B in which diffracted light can bereceived is shown in FIG. 21 and the range B is obtained by using the 70nm generation DRAM having 2F being 0.14 μm and by considering actuallyadapted configurations (for example, to what degree the light having ashort wavelength can be used as incident light or to what degree thetilting section can make an incident angle larger accurately) for thesurface inspecting apparatus 1. For example, diffracted light 123 bcorresponding to the arrangement direction 123 a in the −45 degreedirection occurs at a position near the point of origin (smalldiffraction angle) and, in order to receive the diffracted light 123 b,the wafer 50 is simply rotated toward the direction in which diffractedlight is produced by 45 degrees using the θ rotating section 12 and issimply tilted to have a tilt angle corresponding to a diffraction angleusing the tilting section 13. Also, for example, the diffracted light121 b corresponding to the arrangement direction 121 a in the 0 degreedirection occurs at a position being far from the point of origin (thatis, diffraction angle is large), however, the position is within thediffracted light receiving range B and, therefore, the diffracted lightcan be received. In order to receive the diffracted light 121 b, therotation of the wafer 50 using the θ rotating section 12 is not required(in the same state in FIG. 4A) and setting of the tilt angle is enough,however, due to the large tilt angle, considerable tilting of the wafer50 is required.

FIGS. 22A, 22B, 22C, and 22D show diffracted light distribution inmoving directions in FIG. 21 each corresponding respectively to theazimuth angle at which each of rays of diffracted light corresponding tothe arrangement direction 123 a in the −45 degree direction, arrangementdirection 124 a in the 45 degree direction, arrangement direction 126 ain the 18 degree direction, and arrangement direction 121 a in the 0degree direction is received. Moreover, the left end point in each ofFIGS. 22A to 22D is a point of origin (0th order diffracted light) andthe range from the left end to a broken line is the diffracted lightreceiving range B. For example, as shown in FIG. 22A, it is understoodthat, at the azimuth angle at which the diffracted light 123 bcorresponding to the arrangement direction 123 a in the −45 degreedirection is received, a plurality of rays of diffracted light, exceptsthe diffracted light 123 b surrounded by a circle, is produced dependingon the diffraction angle (corresponding to a horizontal direction). Thatis, it is also understood that, when the arrangement model of the bitcontact 75 shown in FIG. 20 is evaluated by making the diffracted lightsimulator section 48 perform the FFT processing, actually, various raysof diffracted light are produced in various repeating directions. Thisis because high order diffracted light having a specified repeatingpitch is contained. These rays of diffracted light appear also in FIG.21, however, for easy explanation, their illustrations are omitted.

The inspecting condition determining section 45 inputs conditions(azimuth and tilting angle) for obtaining diffracted light from thearrangement direction 123 a in the −45 degree direction, as inspectingconditions, into the inspecting condition setting section 42, which thenrotates the wafer 50 using the θ rotating section 12 toward thedirection in which the diffracted light from the arrangement directionin the −45 degree direction can be received and continuously changes(tilts the wafer continuously) the tilt angle within the diffractedlight receivable range B using the tilting section 13 so that some raysof diffracted light can be received at a specified azimuth. The image ofthe FEM wafer 110 obtained at a plurality of tilt angles enabling thereceipt of diffracted light is obtained using the FEM wafer 110described above and the FEM evaluating section 43, using the same methodemployed in FIGS. 17 to 19, evaluates a tilt angle being sensitive tothe CD value change and determines inspecting conditions (tilt angle)for inspecting the wafer 50 to be inspected. The FEM evaluating section43 outputs the determined inspecting condition to the inspectingcondition setting section 42, which operates the θ rotating section 12and tilting section 13 so that the determined inspecting conditions(azimuth and tilt angle) are set.

Furthermore, when the image of the FEM wafer 110 at a plurality of tiltangles is to be obtained, images are acquired for every differentwavelength by the wavelength selecting section 22 and the wavelength andtilt angle being sensitive to the CD value change may be evaluated bythe FEM evaluating section 43 to determine inspecting conditions(wavelength and tilt angle) for inspecting the wafer 50.

After determining the arrangement direction (arrangement direction 123 aor the −45 degree direction in the bit contact 75) in which diffractedlight is obtained, without using the FEM wafer 110 and FEM evaluatingsection 43, by using the same method employed in FIGS. 14A, 14B, and 14Cto 16, the CD value change may be set by the CD value change convertingsection 47 and the FFT processing is performed by the diffracted lightsimulator section 48 on a design CD value (non-defective model) andchange CD value to obtain diffracted light being sensitive to the CDvalue change and to determine inspecting conditions for receiving thediffracted light.

Thus, according to the present embodiment, the simulation of a change inamounts of diffracted light is performed in a manner to match a change(change in CD values) in shape of a hole pattern (such as bit contact 75or the like) and, therefore, the optimum inspecting conditions can bedetermined according to quantitative judgment criteria. In the case ofDRAM in particular, there are many arrangement directions compared withflash memories or the like, the present invention is effective.Furthermore, the inspecting conditions can be determined from theviewpoint of sensitivity to the CD value change, thus enabling matchingwith the CD values in the semiconductor manufacturing processes to beeasily achieved.

Moreover, the present invention is effective in the inspection of notonly bit contacts but also cell contacts 70, capacitor contacts 85, andcylinders 90 and also in the inspection of field processes. FIG. 23 is adiagram obtained by modeling the capacitor contacts 85 shown in FIG. 11and shows that the inspecting conditions can be determined by the samemethod employed in the above embodiment. FIG. 23 shows that thecapacitor contacts 85 have the arrangement direction 131 a in the 0degree direction, arrangement direction 132 a in the 90 degreedirection, arrangement direction 133 a in the −45 degree direction,arrangement direction 134 a in the 45 degree direction, arrangementdirection 135 a in the 72 degree direction, and arrangement direction136 a in the 18 degree direction.

FIG. 24 is a diagram obtained by performing FFT processing on the modelin FIG. 23 using the diffracted light simulator section 48 and bydisplaying a region near to its point of origin in an enlarged manner.In FIG. 24, rays of diffracted light 131 b to 136 b are shown eachcorresponding respectively to the arrangement direction 131 a in the 0degree direction, arrangement direction 131 a in the 90 degreedirection, arrangement direction 133 a in the −45 degree direction,arrangement direction 134 a in the 45 degree direction, arrangementdirection 135 a in the 72 degree direction, and arrangement direction136 a in the 18 degree direction. As is apparent from FIG. 24, thediffracted light 134 b corresponding to the arrangement direction in the45 degree direction cannot be received since the diffracted light occursout of the diffracted light receiving range B.

FIGS. 25A, 25B and 25C show diffracted light distribution in movingradius directions in FIG. 24, each corresponding respectively to theazimuth angle at which each of rays of diffracted light corresponding tothe arrangement direction 133 a in the −45 degree direction, arrangementdirection 135 a in the 72 degree direction, and arrangement direction131 a in the 0 degree direction is received. As is understood from FIG.25A, at the azimuth angle at which the diffracted light 133 bcorresponding to the arrangement direction 133 a in the −45 degreedirection, a plurality of diffracted light is produced according to adiffraction angle (corresponding to a horizontal direction) excepts thediffracted light 133 b surrounded by a circle.

FIG. 26 is a diagram obtained by modeling the cell contact 70 shown inFIG. 8 and inspecting conditions can be determined using the processemployed in the above embodiment. As shown in FIG. 26, the cell contact70 has an arrangement direction 141 a in the 0 degree direction,arrangement direction 142 a in the −45 degree direction, arrangementdirection 143 a in the 72 degree direction, and arrangement direction144 a in the 31 degree direction.

FIG. 27 is a diagram obtained by performing FFT processing on the modelin FIG. 26 using the diffracted light simulator section 48 and bydisplaying a region near to its point of origin in an enlarged manner.In FIG. 27, rays of diffracted light 141 b to 144 b are shown eachcorresponding respectively to the arrangement direction 141 a in the 0degree direction, arrangement direction 142 a in the −45 degreedirection, arrangement direction 143 a in the 72 degree direction, andarrangement direction 144 a in the 31 degree direction. As is apparentfrom FIG. 27, the diffracted light 142 b corresponding to thearrangement direction 142 a in the −45 degree direction and diffractedlight 144 b corresponding to the arrangement direction 144 a in the 31degree direction cannot be received since these rays of diffracted lightoccur out of the diffracted light receiving range B. The rays ofdiffracted light 141 b and 143 b each corresponding respectively to thearrangement direction 141 a in the 0 degree direction and thearrangement direction 143 a in the 72 degree direction can be received.

FIGS. 28A, 28B, 28C, and 28D show diffracted light distribution inmoving radius directions each corresponding respectively to the azimuthangle at which each of rays of diffracted light corresponding to thearrangement direction 143 a in the 72 degree direction, arrangementdirection 141 a in the 0 degree direction, arrangement direction 142 ain the −45 degree direction, arrangement direction 144 a in the 31degree direction is received. As is apparent from FIGS. 28A to 28D, nodiffracted light occurs (within the diffracted light receiving range B)other than the diffracted light surrounded by a circle. That is, it isunderstood that, in the cell contact 70, only the arrangement direction141 a in the 0 degree direction and arrangement direction 143 a in the72 degree direction can be set as the inspecting conditions.

As described above, in the conventional inspecting apparatus, only thearrangement direction in the 0 degree direction and arrangementdirection in the 90 degree direction can be set. This is becausearrangement information has not been used for condition setting in theconventional apparatus. As a result, in the cell contact 70, theinspecting condition for receiving only diffracted light from thearrangement direction in the 0 degree direction has been set. However,in the case of DRAM manufactured by a process for higher device density,when the cell contact is proportionally contracted, the inspection isimpossible according to the inspecting conditions set only for thearrangement direction in the 0 degree direction.

FIG. 29 is a diagram showing a model obtained by contracting the cellcontact 70 by about 20% and FIG. 30 is a diagram obtained by performingFFT processing using the diffracted light simulator section 48 and bydisplaying a region near to a point of origin in an enlarged manner. Asis apparent from FIG. 30, out of rays of diffracted light 151 b to 154 beach corresponding respectively to the arrangement direction 151 a inthe 0 degree direction, arrangement direction 152 a in the −45 degreedirection, arrangement direction 153 a in the 72 degree direction,arrangement direction 154 a in the 31 direction, only the diffractedlight 153 b corresponding to the arrangement direction 153 a in the 72degree direction can be received. This is also apparent from thediffracted light distribution in the moving radius direction in FIG. 30shown in FIGS. 31A to 31D.

FIG. 32 is a diagram showing an arrangement direction and repeatingpitch to be applied to the cell contact shown in FIG. 8. Here, 2F=0.14μm. FIG. 32 shows that, in the arrangement direction in 72 degreedirection, the repeating pitch is about 0.18 μm which is large comparedwith other arrangement directions. Therefore, even if the repeatingpitch is contracted by about 20%, the repeating pitch becomes 0.144[(0.18×0.8)=0.144] μm and is still within the diffracted light receivingrange. That is, in the cell contact 70, the arrangement directionallowing the repeating interval of holes adjacent to one another to belargest is preferably set as the inspecting conditions.

It has been already described that the cell contact 70 is elliptical andits short diameter director is the arrangement direction 72 a in the 72degree direction (see FIG. 8). On the other hand, in the model of thecell contact 70 as shown in FIGS. 26 and 29, its elliptical shape andits duty (the size of the ellipse, ratio regarding an interval betweenellipses adjacent to one another), direction of the ellipse, that is arelation between short diameter direction and arrangement are not takeninto consideration. By using the shape information being near to anactual state as arrangement information and by evaluating the diffractedlight using the diffracted light simulator section 48, in some cases,1st order diffracted light and higher order are produced from therepeating pitch having a longer period. It is preferable that thediffracted light is evaluated using the arrangement being near to theactual state and its embodiment is described later.

As described above, so far as the critical process only is concerned, inthe processes of manufacturing the DRAM, in order from a lower layer,the field process, gate process, cell contact process, pit contactprocess, bit line process, capacitor contact process, and cylinderprocess are included. That is, the cell contact process includes a gateprocess (various kinds of implant processes intervene therebetween) and,as shown in FIG. 7, the gate 65 has its arrangement direction in the Xdirection (arrangement direction in the 0 degree direction) and has itsrepeating direction in the Y direction. The inspecting condition for thegate 65 is uniquely the condition for receiving diffracted light in theX direction (arrangement direction in the 0 degree direction). The useof illumination light having a wavelength and resist refractive indexthat receives only the signal (diffracted light) of a completelyuppermost layer is ideal, however, in actuality, in some cases, theillumination light transmits through the lower layer and the inspectionis influenced by the lower layer (signal). In some cases, the signalfrom the lower layer has doughnut-shaped luminance unevenness in imageson the entire wafer and luminance unevenness occurs for every exposureshot. These phenomena including luminance unevenness occur more or lessin all processes and, therefore, the non-defective wafer image A1 orinspection image A2 shown in FIG. 3 cannot avoid the influence of theoccurrence of these phenomena. As a result, the inspection of defectswith sufficient detection sensitivity becomes impossible. As the waferbecomes increasingly fine and minute, the resist thickness tends to bethin and it is no exaggeration to say that its lower layer is seen in atransparent manner.

Therefore, when the cell contact 70 is inspected, it is preferable thatthe inspecting condition for the arrangement direction in the 0 degreedirection is avoided. Thus, the arrangement direction of the gate 65existing in the lower layer is the X direction (arrangement direction inthe 0 degree direction) and, therefore, by setting the inspectingcondition so that the diffracted light having an angle being differentfrom the above angle is received, the diffracted light from the gate 65in the lower layer is not received, thus enabling the avoidance of theinfluence by the lower layer. As a result, the image of a non-defectivewafer without luminance unevenness and inspected image can be obtainedwhich enables great improvement of detection sensitivity. This meansthat, even when the resist becomes thin or when self layout is changeddue to higher density, the inspection can be made according to optimuminspecting conditions.

Next, a modified example of the inspecting condition determining sectionis described. The inspection determining section 245 of the modifiedexample, as shown in FIG. 33, is made up of an arrangement datainputting section 246, an SEM image correcting section 247 connectedelectrically with the arrangement data inputting section 246, a CD valuechange/diffracted light simulator section 248 connected electricallywith the SEM image correcting section 247, and an inspecting conditiondata outputting section 249 connected electrically with the CDvalue/change diffracted light simulator section 248.

Into the arrangement data inputting section 246 is inputted and storeddesign data (CAD data or the like) of a reticle as arrangementinformation. The reticle (not shown) is equivalent to an original plateused when a circuit pattern is exposed on the wafer 50 and alight-transmitted portion and light-shielded portion are formed on aglass plate so as to be four times larger in size than the size of awafer. Moreover, the reticle is EB (Electron-Beam)-drawn based on thedesign data. However, in fine and minute patterns formed by the criticalprocess, even if the pattern is rectangular on the recticle, thepattern, when being exposed on the wafer 50, becomes rectangular withrounded corners and, in many cases, elliptical. Furthermore, a squareshape on the reticle becomes circular on the wafer. There are tworeasons for that. The first reason is related to a problem of EB drawingresolution and/or etching accuracy at the time of the formation of thereticle and the second reason is related to an optical problem aboutaberrations in image formation and/or optical proximity correction atthe time of exposure. Therefore, when design data of the reticle is usedfor the diffracted light simulation such as FFT processing, there is analienation between design data of the reticle and data on the diffractedlight from an actual wafer 50.

According to the present embodiment, two kinds of information describedbelow is used. Firstly, macro values applied to CAD data (based ondesign coordinates) of the reticle are utilized. For example, in thecell contact process, the central coordinates of a hole, its arrangementdirection, and values of pitches are used. The central coordinates ofthe hole, its arrangement direction, and values of pitches are notinfluenced by the accuracy of a reticle and image formation and,therefore, these values are used as they are.

Secondly, micro values applied to CD value measurement data obtainedusing the SEM (based on wafer measurement values) are used. That is,reticle accuracy, image formation accuracy, and CD values (including ataper and the like) that may be influenced in the process are used.These values are actually measured values including variations and, forexample, in the cell contact process, actual states of long and shortdiameters of an elliptical hole can be reflected. In addition,information about a bottom, top, and depth is contained. However, if theactual measurement of the depth of a hole is difficult, a designed valueis used instead.

As described above, macro values of the CAD data of the reticle areinputted, as arrangement data, to the arrangement data inputting section246 and the SEM image correcting section 247 makes corrections to thesemacro values so as to come near to values of the pattern on the wafer50. For example, the SEM image correcting section 247 uses a diameter ofan upper surface (top) and a diameter of a bottom surface (bottom) as along diameter and short diameter of an elliptic hole, based on theinformation obtained by measuring the cell contact hole using the SEM.This method is not limited to the cell contact hole. In the case of aDRAM, its resist is thicker compared with a flash memory or the likeand, therefore, a hole has a comparatively large depth. As a result, asan unconscious case, there are some cases in which a hole has a taperedshape. For example, a cylinder has a large depth and is taperedaccordingly. Even in the case of the cell contact, in some cases, itstop diameter is 120 nm and its bottom diameter is 70 nm. Therefore, theSEM image correcting section 247 uses the information about diameters ofthe top and bottom of the hole as correcting information.

Furthermore, it is preferable to use, as information corresponding to CDtolerance values to be stipulated from viewpoints of process management,for example, SEM information about a CD value obtained at the time ofbest focus, CD value within the very possible tolerance, and CD valueplainly out of tolerance. In the line and space pattern, from viewpointsof process management, a change in a line width presents a first problemat the time of the occurrence of defocus and, therefore, the CD value(top and bottom) obtained at the time is preferably used. Moreover, afactor of the CD value change caused by a change in film thickness maybe considered as the additional factor.

As the CD value change/diffracted light simulator 248, “DiffractMOD”being an optical diffraction calculation engine manufactured by RSoftDesign Group Corp. can be suitably used. The “DiffractMOD” allows anellipse to be inputted as if a graphic is drawn and not only supports atapered shape and three dimensional structure but also calculatesdiffracted light produced by swinging change factors such as a CD changeand/or thickness change as a parameter. Naturally, a slanted incidentstate can be considered and, therefore, an arrangement direction beingmost sensitive to the CD value change, out of arrangement directionsthat can be selected, can be determined.

The method for determining conditions for inspection using suchinspecting condition determining section 245 as described above isdescribed by referring to FIGS. 34A, 34B, and 34C. FIG. 34A shows a bitcontact model and the central coordinates or arrangement direction ofthe contact hole is obtained by calculating the CAD data of the reticleinputted into the arrangement data inputting section 246 and dimensionsof the elliptical shape, depth, and tapered portion of the contact holeare obtained by being corrected by the SEM image correcting section 247based on results from measurement using the SEM. FIG. 34A shows a modelin a non-defective state. Further, as described above, the bit contact75 has an arrangement direction 121 a in the 0 degree direction,arrangement direction 122 a in the 90 degree direction, arrangementdirection 123 a in the −45 degree direction, arrangement direction 124 ain the 45 degree direction, arrangement direction 125 a in the 72 degreedirection, and arrangement direction 126 a in the 18 degree direction.

FIG. 34B shows a model obtained by making a correction using the SEMimage correcting section 247 based on results from the measurement bythe SEM when CD values are changed within a tolerance range. That is,FIG. 34B is the model within the very possible tolerance.

FIG. 34C shows a model obtained by making a correction using the SEMimage correcting section 247 based on results from the measurement bythe SEM when CD values are changed greatly to a degree to which the CDvalues becomes out of the tolerance. That is, FIG. 34C shows a modelbeing out of a range of tolerance.

Next, when these models produced by the arrangement data inputtingsection 246 and SEM image correcting section 247 are evaluated by makingthe CD value change/diffracted light simulator section 248 perform FFTprocessing, results shown in FIGS. 35A, 35B, and 35C are obtained eachcorresponding respectively to FIGS. 34A, 34B, and 34C. Moreover, in FIG.35A, rays of diffracted light 121 b to 126 b are displayed eachcorresponding respectively to the arrangement direction 121 a in the 0degree direction, arrangement direction 122 a in the 90 degreedirection, arrangement direction 123 a in the −45 degree direction,arrangement direction 124 a in the 45 degree direction, arrangementdirection 125 a in the 72 degree direction, and arrangement direction126 a in the 18 degree direction. FIG. 36 is a diagram obtained byevaluating the changes in amounts of diffracted light relative to the CDvalue change in the diffracted light corresponding to the arrangementdirection 121 a in the 0 degree direction, arrangement direction 123 ain the −45 degree direction, arrangement direction 124 a in the 45degree direction, and arrangement direction 125 a in the 72 degreedirection.

FIG. 36 is a diagram showing changes of amounts of diffracted lightrelative to the CD change (in FIGS. 35B and 35C) with an amount ofdiffracted light in a non-defective mode in the case in FIG. 35A beingset to be 1. The results show that the amount of diffracted lightchanges most sensitively to the CD value change in the arrangementdirection in the −45 degree direction and the amount of diffracted lightchanges little in the arrangement direction in the 72 degree direction.The amount of diffracted light changes sensitively to the CD valuechange in order of the arrangement direction in the −45 degreedirection, arrangement direction in the 45 degree direction, arrangementdirection in the 0 degree direction, and arrangement direction in the 72degree direction. That is, high detection sensitivity can be expected inthis order. These results can be used as conditions for inspection.

When such evaluation as shown in FIGS. 35A, 35B, and 35C is performed byusing the CD value change/diffracted light simulator section 248, it ispreferable to use light having a plurality of selectable wavelengths λ,for example, an e-line (λ=546 nm), g-line (λ=436 nm), h-line (λ=405 nm),j-line (λ=313 nm) and light having a wavelengthλ=about 250 nm forevaluation. As a result, the optimum wavelength and optimum azimuthangle can be determined. The inspecting condition is not necessarily oneoptimum condition and may be a plurality of conditions. The preferreddegree may be converted into numbers as a score and, for example, inorder of higher scores (most preferable level to slightly preferablelevel), the score may be contained in condition data for inspection.

For example, first two arrangement directions (arrangement direction inthe −45 degree direction and arrangement direction in the 45 degreedirection), out of four preferable arrangement directions, are used anda plurality of inspecting condition data is set so that two rays oflight including j-line (λ=313 nm) and light (λ=near 250 nm) asillumination light and the condition data for inspection may be inputtedfrom the inspecting condition data outputting section 249 to theinspecting condition setting section 42. By performing the inspection ofthe bit contact according to a plurality of conditions for inspectionand by judging that the wafer 50 to be inspected has a defect when evenone result shows the existence of the detect out of inspection resultsobtained from a plurality of conditions for inspection, a failure ofdetecting defects is decreased and detection reliability can beimproved. Moreover, as described above, by selecting an arrangementdirection being different from the arrangement direction of a lowerlayer, signals from the lower layer can be excluded. To realize theexclusion, weights can be assigned to the arrangement direction. Thatis, if there is an arrangement direction from which a relation with thelower layer is desired to be excluded, by considering and adding theinformation about the above arrangement direction to evaluation resultsby the diffracted light simulator section 248 to produce the inspectingcondition data.

Furthermore, according to the inspecting condition determining section245 of the modified example, the setting of inspecting conditionswithout using the wafer (waferless inspecting condition setting) is madepossible. More concretely, the inspecting condition setting as aninitial recipe is made possible by obtaining arrangement information(arrangement direction and repeating pitch) stored in CAD data or thelike from the outside (office or the like) before the test on a wafer bya surface inspecting apparatus in a clean room and by performingevaluation using the CD value change/diffracted light simulator section248. Particularly, at the first stage of development of a new product,under the nominal purpose of proposal conditions including the proposalof conditions for exposure and/or proposal of conditions for a processapparatus, the measurement of CD values using the SEM is frequentlymade, however, it is after such proposal of conditions that theinspection of wafers to be manufactured in quantity is required.However, the start of mass production of the wafer has to be realized atan early stage and the condition setting for the inspection for massproduction wafer has to be performed for a short period. For thispurpose also, the waferless inspecting condition setting is effective.Moreover, within a period of the condition proposal, measurement data ofCD values using the SEM is accumulated gradually, thus improving theaccuracy of evaluation by simulation.

In the present invention, the inspection is performed on the bit contact75, however, the present invention is not limited to this and iseffective not only in the cell contact 70 but also the capacitor contact85 or cylinder 90 and further effective for the inspecting conditionsetting in the field process shown in FIG. 6. In FIG. 6, it is easilyunderstood from the arrangement that a large amount of diffracted lightmay be obtained in the arrangement direction 62 a in the 72 degreedirection, however, it is not clear whether diffracted light occurs inthe repeating arrangement other than the arrangement direction describedabove.

FIG. 37 is a diagram obtained by modeling the field process in FIG. 6.It is understood from FIG. 37 that the active area 60 has thearrangement direction 161 a in the 0 degree direction, arrangementdirection 162 a in the 90 degree direction, arrangement direction 163 ain the −45 degree direction, and arrangement direction 164 a in the 72degree direction.

FIG. 38 is a diagram obtained by performing FFT processing on the modelin FIG. 37 using the CD value change/diffracted light simulator section248 and by displaying a region near to its point of origin in anenlarged manner. In FIG. 38, rays of diffracted light 161 b to 164 b aredisplayed each corresponding respectively to the arrangement direction161 a in the 0 degree direction, arrangement direction 162 a in the 90degree direction, arrangement direction 163 a in the −45 degreedirection, and arrangement direction 164 a in the 72 degree direction.As is apparent from FIG. 38, each of the rays of diffracted light 161 bto 164 b corresponding to four arrangement directions is within thediffracted light receiving range B. It is also understood that the 1storder diffracted light and 2nd order diffracted light corresponding tothe arrangement direction in the −45 degree direction are within thediffracted light receiving range B.

Conditions, out of above conditions, being sensitive to the CD valuechange can be selected in the same ways as above by using the CD valuechange/diffracted light simulator 248. In the above methods, simulationis preferably performed in a manner to be suitably applied to the CDvalue change liable to occur at time of exposure and to the CD valuechange desired to be severely controlled. For example, when the CD valuechange in the long diameter direction of the active area 60 is desiredto be severely managed compared with the CD value change in the shortdiameter direction of the active area 60, the azimuth condition in whichthe amount of diffracted light changes in a manner to be sensitive tothe CD value change in the long diameter direction is preferably foundout.

Or, by fabricating an FEM wafer in the field process and by obtainingwafer images according to a plurality of diffracted light receivingconditions, the inspecting conditions being sensitive to defocus may bedetermined. Even in the case of the bit contact described before, thesame procedures may be selected.

In addition, in the embodiment described above, the case is described byusing the DRAM as an example, however, the present invention is notlimited to these and can be applied to other semiconductor devices suchas a flash memory.

Next, the gate process of a NAND-type flash memory is described byreferring to FIGS. 39A and 39B. In the gate process of the flash memory,as shown in FIG. 39A, 16 pieces of control gates 170 and a select gate171 are disposed among the control gates 170. FIG. 39B shows an FETimage which corresponds to the above disposition. In a leading-edgeflash memory, F=40 to 50 nm and diffracted light 170 a from the controlgate 170 having a 2F pitch is out of the diffracted light receivingrange B. However, (1st order) diffracted light 171 a and higher orderdiffracted light, as shown in FIG. 39B, exist within the diffractedlight receiving range B. Out of these rays of diffracted light, thediffracted light being most sensitive to the CD value change can bedetermined by the same way as described. Moreover, a NOR-type flashmemory has a layout different from the NAND-type flash memory, however,by the same ways as described above, inspecting conditions beingsensitive to the CD value change can be set.

As shown in FIG. 40, a gate line drawing portion 181 is disposed,without exception, at an end of the gate line 180 of the NAND-type flashmemory. The gate line drawing portion 181 has a shape like a head of agolf club being larger than a line width of the gate line 180 and is soconfigured as to keep contact with higher layers. Therefore, the gateline drawing portion 181 has an arrangement being slanted relative tothe repeating arrangement direction of the gate line 180 and therepeating direction of each of the arrangements 182 and 183 is alsoslanted relative to the repeating arrangement direction of the gate line180. The gate line drawing portion 181 is not a contact hole, however,sine the arrangements 182 and 183 of the gate line drawing portion 181are made slanted relative to the repeating arrangement direction of thegate line 180, as if the arrangement is an arrangement of theabove-described contact hole, diffracted light can be obtained at thepitch of a repeating cycle 184 of each of the arrangements 182 and 183.

Furthermore, in an exposure machine, priority is given to repeatabilityof the gate line 180 to be exposed and optimization is performed on aphase-shifting method and a modified illumination method. Therefore,when an error such as defocus occurs in the exposure machine, a patternbeing isolated from the gate line 180 is easily affected by the defocusand a defect such as pattern falling is liable to occur in the gate linedrawing section 181 rather than the gate line 180. Thus, in the surfaceinspecting apparatus of the present invention, sensitive detection ofdefects in not only the gate line 180 but also the gate line drawingsection 181 is necessary. To achieve this, the setting of diffractionconditions is preferred so that diffracted light corresponding to therepeating cycle 184 of each of the arrangements 182 and 183 can beobtained and a wafer can be rotated and the CD value change can bedetected sensitively. Even in such processes of semiconductor productionas described above, it is possible to avoid an influence by a backingcaused by a difference in the azimuth angle of diffracted light(arrangement direction of patterns).

In a logic device, though its repeating arrangement region area ratio ina semiconductor chip is small, unlike various memories, the inspectionof defects using diffracted light has been applied. However, even in thesame manufacturing process, since arrangement directions of patterns andrepeating pitches corresponding to a plurality of arrangement regionsexist, it was difficult to determine inspecting conditions correspondingto each of arrangement directions. Unlike the conventional technology,according to the present invention, diffraction simulation using thearrangement CAD data is possible and, therefore, easy determination ofinspecting conditions is realized.

Additionally, the defect inspection of the present invention can beapplied not only to semiconductor wafers but also to products having arepeating arrangement pattern such as a reticle. It has been alreadydescribed that the reticle pattern is drawn based on designing data and,according to EB drawing accuracy, even if the pattern is of a rectangleshape according to a viewpoint of designing, the reticle patternactually comes to be round. The present invention can be applied to theinspection of the degree of roundness of an object to be inspected. Thatis, the technology of the present invention can be easily understood bythinking in a manner in which the CD value change is replaced with thedegree of roundness of a reticle pattern, change in a rectangularchange, change in line width or the like. By evaluating the arrangementdirection and/or repeating pitch being sensitive to these changes and bysetting the arrangement direction and/or repeating pitch as inspectingconditions, a product having a shape (roundness) change in the patternof the reticle or large dimensional changes can be detected as a defect.

EXPLANATION OF NUMERALS AND CHARACTERS

1: Surface inspecting apparatus, 20: Illuminating section, 25:Illumination light, 30: Detecting section, 35: Diffracted light, 40:Image processing section, 41: Inspecting section, 42: Inspectingcondition setting section, 43: FEM evaluating section, 45: Inspectingcondition determining section, 50: Wafer (semiconductor substrate), 60:Active area (hole pattern), 65: Gate (line pattern), 70: Cell contact(hole pattern), 75: Bit contact (hole pattern), 80: Bit line (linepattern), 85: Capacitor contact (hole pattern), 90: Cylinder (holepattern), 245: Inspecting condition determining section (modifiedexample)

1. A surface inspecting method for inspecting a surface of a semiconductor substrate having a line-shaped line pattern and a hole-shaped hole pattern formed on the line pattern, each being arranged repeatedly, comprising: a first step of setting an irradiating direction of illumination light on a surface of the semiconductor substrate; a second step of irradiating the surface of the semiconductor substrate with illumination light from the irradiating direction set at the first step; a third step of detecting diffracted light corresponding to a bit of the hole pattern from the surface irradiated with the illumination light; and a fourth step of detecting existence/non-existence of a defect occurring in the hole pattern based on the diffracted light detected at the third step; in the first step, the irradiating direction being set so that a traveling direction of the illumination light on the surface of the semiconductor substrate is different from a repeating arrangement direction of the line pattern and substantially matches a repeating arrangement direction of the hole pattern.
 2. The surface inspecting method according to claim 1, wherein, in the first step, the irradiating direction is set so that a travelling direction of the illumination light on the surface of the semiconductor substrate is different from the repeating arrangement direction of the line pattern and the diffracted light an amount of which greatly changes depending on a change in a shape of the hole pattern occurs.
 3. The surface inspecting method according to claim 2, wherein, in the first step, the irradiating direction is set by performing simulation of a change in an amount of the diffracted light according to a change in shape of the hole pattern based on designing information of the hole pattern or shape measurement information of a hole pattern whose shape has been measured in advance.
 4. A surface inspecting method for inspecting a surface of a semiconductor substrate having a hole-shaped pattern, comprising: a first step of setting an irradiating direction of an illumination light to be applied to a surface of the semiconductor substrate; a second step of irradiating the surface of the semiconductor substrate with illumination light from the irradiating direction set at the first step; a third step of detecting diffracted light corresponding to a pitch of the hole pattern to be applied from the surface irradiated with the illumination light; a fourth step of inspecting existence/non-existence of a defect in the hole pattern based on the diffracted light detected at the third step, and in the first step, the irradiating direction being set by performing simulation of a change in an amount of diffracted light according to a change in shape of the hole pattern so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs.
 5. The surface inspecting method according to claim 4, wherein, in the first step, simulation of a change in an amount of the diffracted light is performed according to a change in shape of the hole pattern based on one of designing information about the hole pattern and shape measurement information about a hole pattern whose shape has been measured in advance.
 6. The surface inspecting method according to claim 4, wherein, in the first step, the irradiating direction is set so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs and that diffracted light is not easily produced form a layer on a side being lower than the hole pattern.
 7. A surface inspecting apparatus for inspecting a surface of a semiconductor substrate having a line-shaped line pattern and a hole-shaped hole pattern formed on the line pattern, comprising: a setting section to set an irradiating direction of illumination light on a surface of the semiconductor substrate; an illuminating section to irradiate the surface of the semiconductor substrate with illumination light from the irradiating direction set by the setting section; a detecting section to detect diffracted light corresponding to a bit of the hole pattern from the surface irradiated with the illumination light; an inspecting section of detecting existence/non-existence of a defect occurring in the hole pattern based on the diffracted light detected by the inspecting section; and the setting section setting the irradiating direction so that a traveling direction of the illumination light on the surface of the semiconductor substrate is different from a repeating arrangement direction of the line pattern and substantially matches a repeating arrangement direction of the hole pattern.
 8. The surface inspecting apparatus according to claim 7, wherein the setting section sets the irradiating direction so that the travelling direction of the illumination light on the surface of the semiconductor substrate is different from the repeating arrangement direction of the line pattern and the diffracted light an amount of which greatly changes depending on a change in a shape of the hole pattern occurs.
 9. The surface inspecting apparatus according to claim 8, wherein the setting section sets the irradiating direction by performing simulation of a change in an amount of the diffracted light according to a change in shape of the hole pattern based on one of designing information about the hole pattern and shape measurement information about a hole pattern whose shape has been measured in advance.
 10. A surface inspecting apparatus for inspecting a surface of a semiconductor substrate having a hole-shaped pattern, comprising: a setting section to set an irradiating direction of an illumination light to be applied to a surface of the semiconductor substrate; an illuminating section to irradiate a surface of the semiconductor substrate with illumination light from the irradiating direction set by the setting section; a detecting section to detect diffracted light corresponding to a pitch of the hole pattern to be applied from the surface irradiated with the illumination light; an inspecting section to inspect existence/non-existence of a defect in the hole pattern based on the diffracted light detected by the detecting section, and the setting section setting the irradiating direction by performing simulation of a change in an amount of diffracted light according to a change in shape of the hole pattern so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs.
 11. The surface inspecting apparatus according to claim 10, wherein the setting section performs simulation of a change in an amount of the diffracted light according to a change in shape of the hole pattern based on one of designing information about the hole pattern and shape measurement information about a hole pattern whose shape has been measured in advance.
 12. The surface inspecting apparatus according to claim 10, wherein the setting section sets the irradiating direction so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs and that diffracted light is not easily produced form a layer on a side being lower than the hole pattern.
 13. The surface inspecting method according to claim 5, wherein, in the first step, the irradiating direction is set so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs and that diffracted light is not easily produced form a layer on a side being lower than the hole pattern.
 14. The surface inspecting apparatus according to claim 11, wherein the setting section sets the irradiating direction so that the diffracted light an amount of which changes greatly according to a change in shape of the hole pattern occurs and that diffracted light is not easily produced form a layer on a side being lower than the hole pattern. 